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700 mhz to 1000 mhz, 1 w rf driver amplifier adl5605 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features operation from 700 mhz to 1000 mhz gain of 23 db at 943 mhz oip3 of 44.2 dbm at 943 mhz p1db of 30.9 dbm at 943 mhz noise figure of 4.8 db at 943 mhz power supply: 5 v power supply current: 307 ma typical internal active biasing fast power-up/power-down function compact 4 mm 4 mm, 16-lead lfcsp esd rating of 1 kv (class 1c) pin-compatible with the adl5606 (1800 mhz to 2700 mhz) applications wireless infrastructure automated test equipment ism/amr applications general description the adl5605 is a broadband, two-stage, 1 w rf driver amplifier that operates over a frequency range of 700 mhz to 1000 mhz. the adl5605 operates on a 5 v supply voltage and a supply current of 307 ma. the driver also incorporates a fast power- up/power-down function for tdd applications, applications that require a power saving mode, and applications that intermittently transmit data. the adl5605 is fabricated on a gaas hbt process and is packaged in a compact 4 mm 4 mm, 16-lead lfcsp that uses an exposed paddle for excellent thermal impedance. the adl5605 operates from ?40c to +85c. a fully populated evaluation board tuned to 943 mhz is also available. functional block diagram 09353-001 11 rfout 12 rfout 10 rfout 9rfout 5 n c 6 n c 7 n c 8 n c 1 rfin 2 disable 3 vcc 4 vbias 1 5 n c 1 6 n c 1 4 n c 1 3 n c adl5605 vbias pwdn figure 1. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 2 4 6 8 10121416182022 acpr (dbc) p out (dbm) 09353-002 946mhz figure 2. acpr vs. output power, 3gpp, tm1-64, at 946 mhz
adl5605 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? typical scattering parameters ..................................................... 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? 748 mhz frequency tuning band ............................................. 8 ? 881 mhz frequency tuning band ............................................. 9 ? 943 mhz frequency tuning band ........................................... 10 ? general......................................................................................... 11 ? applications information .............................................................. 13 ? basic layout connections ......................................................... 13 ? adl5605 matching .................................................................... 14 ? acpr and evm ......................................................................... 15 ? thermal considerations ............................................................ 15 ? soldering information and recommended pcb land pattern .......................................................................................... 15 ? evaluation board ............................................................................ 16 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 18 ? revision history 7/11revision 0: initial version
adl5605 rev. 0 | page 3 of 20 specifications vcc1 = 5 v and t a = 25c, unless otherwise noted. 1 table 1. parameter test conditions/comments min typ max unit overall function frequency range 700 1000 mhz frequency = 748 mhz 20 mhz gain 24.3 db vs. frequency 20 mhz +0.01/?0.19 db vs. temperature ?40c t a +85c 0.8 db vs. supply 4.75 v to 5.25 v 0.07 db output 1 db compression point (p1db) 31.4 dbm vs. frequency 20 mhz ?0.68/+0.08 db vs. temperature ?40c t a +85c +0.94/?1.99 db vs. supply 4.75 v to 5.25 v ?0.24/?0.05 db output third-order intercept (oip3) ?f = 1 mhz, p out = 14 dbm per tone 41.9 dbm vs. frequency 20 mhz ?0.22/+0.16 db vs. temperature ?40c t a +85c +0.07/?1.56 db vs. supply 4.75 v to 5.25 v +0.04/+0.09 db noise figure 4.8 db frequency = 881 mhz 13 mhz gain 23.0 db vs. frequency 13 mhz ?0.03/?0.08 db vs. temperature ?40c t a +85c 0.7 db vs. supply 4.75 v to 5.25 v 0.05 db output 1 db compression point (p1db) 31.4 dbm vs. frequency 13 mhz ?0.18/?0.11 db vs. temperature ?40c t a +85c 0.6 db vs. supply 4.75 v to 5.25 v ?0.4/+0.3 db output third-order intercept (oip3) ?f = 1 mhz, p out = 14 dbm per tone 43.4 dbm vs. frequency 13 mhz ?0.32/+0.40 db vs. temperature ?40c t a +85c ?0.19/?0.99 db vs. supply 4.75 v to 5.25 v +0.21/?0.03 db noise figure 4.7 db frequency = 943 mhz 18 mhz gain 23.0 db vs. frequency 18 mhz +0.28/?0.04 db vs. temperature ?40c t a +85c 0.8 db vs. supply 4.75 v to 5.25 v 0.04 db output 1 db compression point (p1db) 30.9 dbm vs. frequency 18 mhz +0.39/?0.08 db vs. temperature ?40c t a +85c +0.7/?0.9 db vs. supply 4.75 v to 5.25 v ?0.43/+0.35 db adjacent channel power ratio (acpr) p out = 18 dbm, one-carrier w-cdma, 64 dpch, frequency = 946 mhz 51 dbc output third-order intercept (oip3) ?f = 1 mhz, p out = 14 dbm per tone 44.2 dbm vs. frequency 18 mhz ?0.47/?0.10 db vs. temperature ?40c t a +85c +0.7/?1.6 db vs. supply 4.75 v to 5.25 v ?0.08/+0.07 db noise figure 4.8 db
adl5605 rev. 0 | page 4 of 20 parameter test conditions/comments min typ max unit power-down interface disable pin logic level to enable v disable decreasing 0 1.1 v logic level to disable v disable increasing 1.4 5 v disable pin current v disable = 5 v 1.4 ma vcc1 pin current 1 v disable = 5 v 5.5 ma enable time 10% of control pulse to 90% of rfout 75 ns disable time 10% of control pulse to 90% of rfout 20 ns power interface rfout pin supply voltage 4.75 5 5.25 v supply current 307 385 ma vs. temperature ?40c t a +85c ?20/+1 ma 1 vcc1 is the supply to the dut through the rfout pins.
adl5605 rev. 0 | page 5 of 20 typical scattering parameters vcc1 = 5 v and t a = 25 c; the effects of the test fixture have been de-embedded up to the pins of the device. 1 table 2. frequency (mhz) s11 s21 s12 s22 magnitude (db) angle () magnitude (db) angle () magnitude (db) angle () magnitude (db) angle () 100 ?2.38 162.05 5.53 133.84 ?48.08 12.48 ?1.30 ?147.53 150 ?2.63 153.17 14.11 95.13 ?47.50 2.17 ?0.55 ?172.43 200 ?2.95 144.23 18.99 67.83 ?55.96 ?119.96 ?0.68 ?173.81 250 ?3.50 135.13 22.75 39.76 ?55.27 52.76 ?1.24 ?171.76 300 ?4.41 127.84 25.46 ?7.79 ?61.09 77.07 ?1.10 ?176.42 350 ?4.58 124.74 23.14 ?63.51 ?61.80 140.72 ?1.06 ?177.13 400 ?5.11 110.20 17.94 ?30.49 ?52.49 171.89 ?1.15 ?176.29 450 ?6.82 108.32 22.16 ?61.71 ?67.98 ?27.39 ?1.11 ?177.02 500 ?7.26 106.20 21.56 ?87.12 ?62.64 ?21.99 ?0.87 ?177.37 550 ?7.66 101.35 20.40 ?105.19 ?61.53 34.70 ?0.92 ?179.14 600 ?8.25 95.77 19.42 ?118.96 ?61.21 99.93 ?0.78 179.80 650 ?8.86 89.58 18.55 ?130.30 ?61.13 129.82 ?0.87 179.43 700 ?9.58 82.66 17.89 ?140.88 ?59.03 107.89 ?0.87 178.46 750 ?10.59 75.33 17.40 ?150.63 ?61.26 91.70 ?0.90 178.01 800 ?11.75 66.62 17.07 ?160.56 ?57.17 92.00 ?0.93 177.54 850 ?13.27 57.13 16.89 ?170.83 ?56.35 107.58 ?0.93 177.22 900 ?15.44 46.13 16.84 178.03 ?56.74 99.86 ?0.96 176.90 950 ?18.94 29.27 16.93 165.27 ?54.82 107.20 ?0.96 176.66 1000 ?26.34 ?2.06 16.96 150.36 ?52.26 73.48 ?0.98 176.43 1050 ?26.92 ?130.02 16.77 132.88 ?54.70 68.96 ?0.94 176.27 1100 ?18.87 ?171.63 16.17 113.62 ?54.77 47.54 ?0.81 176.15 1150 ?15.30 163.88 14.89 94.11 ?53.44 43.95 ?0.76 175.49 1200 ?13.83 145.18 13.13 76.86 ?55.60 11.97 ?0.72 174.79 1250 ?13.51 129.85 11.09 62.33 ?55.37 33.66 ?0.66 173.83 1300 ?13.68 117.81 8.95 50.66 ?57.24 20.12 ?0.68 173.19 1350 ?14.26 108.51 6.91 41.54 ?59.07 24.50 ?0.66 172.57 1400 ?14.96 99.61 4.91 33.49 ?60.44 14.20 ?0.69 171.85 1450 ?15.76 92.58 3.04 26.87 ?61.45 45.66 ?0.63 171.46 1500 ?16.83 86.52 1.23 21.09 ?57.41 62.21 ?0.69 170.87 1550 ?17.90 79.79 ?0.47 16.01 ?62.00 53.37 ?0.66 170.42 1600 ?19.28 73.87 ?2.09 11.40 ?56.83 57.90 ?0.69 169.98 1650 ?20.56 67.65 ?3.63 7.32 ?57.60 58.62 ?0.68 169.51 1700 ?22.42 60.60 ?5.10 3.62 ?59.47 77.96 ?0.68 168.99 1750 ?24.45 51.72 ?6.53 0.23 ?58.70 76.85 ?0.67 168.59 1800 ?26.42 38.39 ?7.92 ?3.05 ?55.11 66.53 ?0.68 168.10 1850 ?28.73 21.43 ?9.27 ?6.05 ?58.19 37.40 ?0.67 167.72 1900 ?29.99 ?4.11 ?10.56 ?8.66 ?61.08 43.12 ?0.68 167.18 1950 ?29.61 ?32.34 ?11.84 ?11.11 ?57.28 78.91 ?0.67 166.94 2000 ?27.80 ?55.73 ?13.07 ?13.38 ?56.29 83.05 ?0.68 166.45 1 vcc1 is the supply to the dut through the rfout pins.
adl5605 rev. 0 | page 6 of 20 absolute maximum ratings table 3. parameter rating supply voltage, vcc1 1 6.5 v input power (50 impedance) 20 dbm internal power dissipation (paddle soldered) 2 w maximum junction temperature 150c lead temperature (soldering 60 sec) 240c operating temperature range ?40c to +85c storage temperature range ?65c to +150c 1 vcc1 is the supply to the dut through the rfout pins. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 4 lists the junction-to-air thermal resistance ( ja ) and the junction-to-paddle thermal resistance ( jc ) for the adl5605 . for more information, see the thermal considerations section. table 4. thermal resistance package type ja jc unit 16-lead lfcsp (cp-16-10) 52.1 12.1 c/w esd caution
adl5605 rev. 0 | page 7 of 20 pin configuration and fu nction descriptions pin 1 indicator 1 rfin 2 disable 3 vcc 4 vbias 11 rfout 12 rfout 10 rfout 9rfout 5 n c 6 n c 7 n c 8 n c 1 5 n c 1 6 n c 1 4 n c 1 3 n c adl5605 top view (not to scale) 09353-003 notes 1. the exposed paddle should be soldered to a low impedance electrical and thermal ground plane. 2. nc = no connect. do not connect to this pin. figure 3. pin configuration table 5. pin function descriptions pin o. mnemonic description 1 rfin rf input. requires a dc blocking capacitor. 2 disable connect this pin to 5 v to disable the part. in the disabled state, the part draws approximately 5 ma of current from the power supply and 1.4 ma from the disable pin. 3 vcc under normal operation, this pin is connected to the power supply and draws a combined 307 ma of current. when this pin is grounded along with the vbias pin, the device is disabled and draws approximately 1.4 ma from the disable pin. 4 vbias applying 5 v to this pin enables the bias circui t. when this pin is grounded, the device is disabled. 5, 6, 7, 8, 13, 14, 15, 16 nc no connect. do not connect to this pin. 9, 10, 11, 12 rfout rf output. dc bias is provided to this pin through an inductor that is connected to the 5 v power supply. the rf path requires a dc blocking capacitor. ep the exposed paddle should be so ldered to a low impedance electr ical and thermal ground plane.
adl5605 rev. 0 | page 8 of 20 typical performance characteristics 748 mhz frequency tuning band 50 45 0 10 5 15 20 30 25 35 40 728 763 733 738 743 748 753 758 768 noise figure, gain, p1db, oip3 (db, dbm) frequency (mhz) 09353-004 oip3 (dbm) p1db (dbm) gain (db) nf (db) figure 4. noise figure, gain, p1db, and oip3 vs. frequency (oip3 at p out = 14 dbm per tone) 28 27 20 21 22 23 24 25 26 728 763 733 738 743 748 753 758 768 gain (db) frequency (mhz) 09353-005 +85c ?40c +25c figure 5. gain vs. fr equency and temperature 0 ?10 ?20 ?30 ?40 ?50 ?60 728 763 733 738 743 748 753 758 768 s-parameters (db) frequency (mhz) 09353-006 s11 s12 s22 figure 6. input return loss (s11), output return loss (s22), and reverse isolation (s12) vs. frequency 42 24 26 28 30 32 34 40 38 36 46 28 30 32 34 36 38 44 42 40 728 733 738 743 748 753 758 763 768 p1db (dbm) oip3 (dbm) frequency (mhz) 09353-007 ?40c +85c +85c +25c +25c ?40c figure 7. p1db and oip3 vs. frequency and temperature (oip3 at p out = 14 dbm per tone) 44 43 42 41 40 39 38 ?2 0 2 4 6 8 1012141618 oip3 (dbm) p out per tone (dbm) 09353-008 768mhz 748mhz 728mhz figure 8. oip3 vs. p out and frequency 7 6 5 4 3 2 738 728 748 758 768 noise figure (db) frequency (mhz) 09353-009 +25c +85c ?40c figure 9. noise figure vs. frequency and temperature
adl5605 rev. 0 | page 9 of 20 881 mhz frequency tuning band 50 45 40 35 30 25 20 15 10 5 0 868 873 878 883 888 893 noise figure, gain, p1db, oip3 (db, dbm) frequency (mhz) 09353-010 oip3 (dbm) p1db (dbm) gain (db) nf (db) figure 10. noise figure, gain, p1db, and oip3 vs. frequency (oip3 at p out = 14 dbm per tone) 27 19 21 20 22 23 24 25 26 868 870 872 874 876 878 880 882 894 892 890888886884 gain (db) frequency (mhz) 09353-011 +85c ?40c +25c figure 11. gain vs. frequency and temperature 0 ?10 ?20 ?30 ?40 ?50 ?60 868 873 878 883 888 893 s-parameters (db) frequency (mhz) 09353-012 s11 s12 s22 figure 12. input return loss (s11) , output return loss (s22), and reverse isolation (s12) vs. frequency 40 26 28 30 32 34 38 36 46 32 34 36 38 44 42 40 868 870 880878876874872 884882 886 888 890 892 894 p1db (dbm) oip3 (dbm) frequency (mhz) 09353-013 +85c ?40c +25c +85c +25c ?40c figure 13. p1db and oip3 vs . frequency and temperature (oip3 at p out = 14 dbm per tone) 45 44 43 42 41 40 39 ?2024681012141618 oip3 (dbm) p out per tone (dbm) 09353-014 868mhz 881mhz 894mhz figure 14. oip3 vs. p out and frequency 7 6 5 4 3 2 878 868 888 noise figure (db) frequency (mhz) 09353-015 +25c ?40c +85c figure 15. noise figure vs . frequency and temperature
adl5605 rev. 0 | page 10 of 20 943 mhz frequency tuning band 50 45 0 10 5 15 20 30 25 35 40 925 930 935 940 945 950 955 960 noise figure, gain, p1db, oip3 (db, dbm) frequency (mhz) 09353-016 oip3 (dbm) p1db (dbm) gain (db) nf (db) figure 16. noise figure, gain, p1db, and oip3 vs. frequency (oip3 at p out = 14 dbm per tone) 19 20 21 22 23 24 25 26 27 925 930 935 940 945 950 955 960 gain (db) frequency (mhz) ?40c +85c +25c 09353-017 figure 17. gain vs. frequency and temperature 0 ?10 ?20 ?30 ?40 ?50 ?60 925 955 930 935 940 945 950 960 s-parameters (db) frequency (mhz) 09353-018 s11 s12 s22 figure 18. input return loss (s11) , output return loss (s22), and reverse isolation (s12) vs. frequency 40 26 28 30 32 34 38 36 48 34 36 38 44 46 42 40 925 930 940 935 945 950 955 960 p1db (dbm) oip3 (dbm) frequency (mhz) 09353-019 ?40c +25c +25c +85c +85c ?40c figure 19. p1db and oip3 vs . frequency and temperature (oip3 at p out = 14 dbm per tone) 46 45 44 43 42 41 40 ?2024681012141618 oip3 (dbm) p out per tone (dbm) 09353-020 925mhz 943mhz 960mhz figure 20. oip3 vs. p out and frequency 7 6 5 4 3 2 930 925 935 940 945 950 955 960 noise figure (db) frequency (mhz) 09353-021 ?40c +85c +25c figure 21. noise figure vs . frequency and temperature
adl5605 rev. 0 | page 11 of 20 general 35 30 0 5 15 10 20 25 43.7 44.4 43.8 43.9 44.0 44.1 44.2 44.3 44.5 44.6 44.7 44.8 percentage (%) oip3 (dbm) 09353-022 figure 22. oip3 distribution at 943 mhz, 14 dbm per tone 35 40 30 0 5 15 10 20 25 30.5 31.1 30.6 30.7 30.8 30.9 31.0 31.2 31.3 31.4 31.5 percentage (%) p1db (dbm) 09353-023 figure 23. p1db distribution at 943 mhz 35 40 30 0 5 15 10 20 25 22.7 23.1 22.8 22.9 23.0 23.2 23.3 23.4 percentage (%) gain (db) 09353-024 figure 24. gain distribution at 943 mhz 35 30 0 5 15 10 20 25 4.45 4.65 4.50 4.55 4.60 4.70 4.75 4.80 percentage (%) noise figure (db) 09353-025 figure 25. noise figure distribution at 943 mhz 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 2 4 6 8 10121416182022 acpr (dbc) p out (dbm) 09353-026 946mhz figure 26. acpr vs. p out , 3gpp, tm1-64, at 946 mhz 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?10 ?5 0 25 20 15 10 5 evm (%) p out (dbm) 09353-027 946mhz figure 27. evm vs. p out , 3gpp, tm1-64, at 946 mhz
adl5605 rev. 0 | page 12 of 20 320 310 280 290 300 ?40 30 ?30?20?100 1020 4050607080 supply current (ma) temperature (c) 09353-028 4.75v 5v 5.25v figure 28. supply current vs. temper ature and supply voltage at 943 mhz 09353-029 ch2 1v ? ch3 1v ? m20ns 10gs/s it 4ps/pt a ch2 2.5v 3 2 figure 29. turn-off time, 10% of control pulse to 90% of rfout 0 9353-030 ch2 1v ? ch3 1v ? m20ns 10gs/s it 4ps/pt a ch2 2.5v 3 2 figure 30. turn-on time, 10% of control pulse to 90% of rfout
adl5605 rev. 0 | page 13 of 20 applications information basic layout connections the basic connections for operating the adl5605 are shown in figure 31 . the rf matching components correspond to the 943 mhz frequency tuning band. power supply the voltage supply for the adl5605 , which ranges from 4.75 v to 5.25 v, should be connected to the vcc1 test pin. the dc bias to the output stage is supplied through l1 and is connected to the rfout pin. three decoupling capacitors (c7, c8, and c9) are used to prevent rf signals from propagating on the dc lines. the vbias and vcc pins can be directly connected to the main supply voltage. additional decoupling capacitors (c5, c6, c11, c12, c13, and c14) are required on the vcc and vbias pins. rf input interface pin 1 is the rf input pin for the adl5605 . the rf input is easily matched to 50 with only one shunt capacitor and the micro- strip line used as an inductor. for the 881 mhz and 943 mhz frequency tuning bands, the input requires no external matching components. for complete information about component values and spacing for the different frequency tuning bands, see the adl5605 matching section. rf output interface pin 9 to pin 12 are the rf output pins. inductor l2, the shunt capacitor, c out , and the inductance from the microstrip line are used to match the rf output to 50 . for complete information about component values and spacing for the different frequency tuning bands, see the adl5605 matching section. power-down the adl5605 can be disabled by connecting the disable pin to 5 v. when disabled, the adl5605 draws approximately 5 ma of current from the power supply and 1.4 ma from the disable pin. decoupling capacitor c3 is recommended to prevent the propagation of rf signals. to completely shut down the device, connect the vcc pin, the vbias pin, and the vcc1 test pin to ground. in this state, the part draws approximately 1.4 ma from the disable pin. rfin vcc v bias disable rfout 12 vbias 11 vcc 10 disable 9 rfin 1 2 3 4 adl5605 vcc1 c out 8pf c2 100pf c1 100pf c3 10pf c5 100pf c7 100pf c8 0.01f c9 10f rfout rfout rfout rfout 09353-031 13 8 14 7 15 6 16 5 nc nc nc nc nc nc nc nc c6 0.01f c11 10f c12 100pf c13 0.01f c14 10f l1 18nh l2 1.6nh figure 31. basic connections
adl5605 rev. 0 | page 14 of 20 adl5605 matching the rf input of the adl5605 can be easily matched to 50 with at most one external component and the microstrip line used as an inductor. the rf output requires one series inductor, one shunt capacitor, and the microstrip line used as an inductor. table 6 lists the required matching component values. capac- itors c in and c out are murata grm155 series (0402 size), and inductor l2 is a coilcraft? 0603cs series (0603 size). for all frequency tuning bands, the placement of c in , l2, and c out is critical. table 7 lists the recommended component spacing for the various frequency tuning bands. the component spacing is referenced from the center of the component to the edge of the package. figure 32 to figure 34 show the matching networks. table 6. recommended components for basic connections frequency (mhz) c in (pf) l2 (nh) c out (pf) 728 to 768 2.4 2.7 12.0 868 to 894 n/a 1.6 8.0 925 to 961 n/a 1.6 8.0 table 7. matching component spacing frequency (mhz) 1 (mils) 2 (mils) 3 (mils) 728 to 768 63 94.5 169 868 to 894 n/a 94.5 268 925 to 961 n/a 94.5 240 rfout 12 11 10 9 rfin 16 1 2 13 14 15 nc nc nc nc rfin rfout rfout rfout rfout disable c in 2.4pf c out 12pf c2 100pf l1 18nh l2 2.7nh c1 100pf 1 3 2 adl5605 09353-032 figure 32. adl5605 match parameters, 748 mhz frequency tuning band rfout 12 11 10 9 rfin 16 1 2 13 14 15 nc nc nc nc rfin rfout rfout rfout rfout disable c in open c out 8pf c2 100pf l1 18nh l2 1.6nh c1 100pf 3 2 adl5605 09353-033 figure 33. adl5605 match parameters, 881 mhz frequency tuning band rfout 12 11 10 9 rfin 16 1 2 13 14 15 nc nc nc nc rfin rfout rfout rfout rfout disable c in open c out 8pf c2 100pf l1 18nh l2 1.6nh c1 100pf 3 2 adl5605 09353-034 figure 34. adl5605 match parameters, 943 mhz frequency tuning band
adl5605 rev. 0 | page 15 of 20 acpr and evm all adjacent channel power ratio (acpr) and error vector magnitude (evm) measurements were made using a single w-cdma carrier and test model 1-64. the signal is generated by a very low acpr source and is meas- ured at the output by a high dynamic range spectrum analyzer. for acpr measurements, the filter setting was chosen for low acpr; for evm measurements, the low evm setting was selected. the spectrum analyzer incorporates an instrument noise correc- tion function, and highly linear amplifiers were used to boost the power levels for acpr measurements. figure 26 shows acpr vs. p out at 946 mhz. for power levels up to 18 dbm, an acpr of 51 dbc or better can be achieved at 946 mhz. figure 27 shows evm vs. p out at 946 mhz. the evm measured is 0.5% for power levels up to 18 dbm at 946 mhz. the baseline composite evm for the signal source was approximately 0.5%. when operated in the linear region, there is little or no contribu- tion to evm by the amplifier. thermal considerations the adl5605 is packaged in a thermally efficient 4 mm 4 mm, 16-lead lfcsp. the thermal resistance from junction to air ( ja ) is 52.1c/w. the thermal resistance for the product was extracted assuming a standard 4-layer jedec board with 25 copper plated thermal vias. the thermal vias are filled with conductive copper paste (ae3030 with thermal conductivity of 7.8 w/mk and thermal expansion 1 of 4 10 ?5 /c and 2 of 8.6 10 ?5 /c). the thermal resistance from junction to case ( jc ) is 12.1c/w, where the case is the exposed pad of the lead frame package. for the best thermal performance, it is recommended that as many thermal vias as possible be added under the exposed pad of the lfcsp. the thermal resistance values assume a minimum of 25 thermal vias arranged in a 5 5 array with a via diameter of 8 mils, via pad of 16 mils, and a pitch of 20 mils. the vias are plated with copper, and the drill hole is filled with a conductive copper paste. for optimal performance, it is recommended that the thermal vias be filled with a conductive paste of the equivalent thermal conductivity specified earlier in this section; alternatively, an external heat sink can be used to dissipate heat quickly without affecting the die junction temperature. it is also recommended that the ground pattern be extended above and below the device to improve thermal efficiency (see figure 35 ). soldering information and recommended pcb land pattern figure 35 shows the recommended land pattern for the adl5605 . to minimize thermal impedance, the exposed paddle on the 4 mm 4 mm lfcsp is soldered to a ground plane along with pin 5 to pin 8 and pin 13 to pin 16. to improve thermal dissi- pation, 25 thermal vias are arranged in a 5 5 array under the exposed paddle. areas above and below the paddle are tied with regular vias. if multiple ground layers exist, they should be tied together using vias. for more information about land pattern design and layout, see the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . 09353-035 rfout rfin 16 mil via pad with 8 mil via 16 13 58 figure 35. recommended land pattern
adl5605 rev. 0 | page 16 of 20 evaluation board the schematic of the adl5605 evaluation board is shown in figure 36. the evaluation board uses 25 mils wide, 50 traces and is made from is410 material with a 20 mils gap to ground. the evaluation board is tuned for operation at 943 mhz. the inputs and outputs should be ac-coupled with appropriately sized capacitors; therefore, for low frequency applications, the value of c1 and c2 may need to be increased. dc bias is provided to the output stage via an inductor (l1) connected to the rfout pin. a bias voltage of 5 v is recommended. the evaluation board has a short, non-50 line on its output to accommodate the four output pins and to allow for easier low inductance output matching. the pads for pin 9 to pin 12 are included on this microstrip line and are included in all matches. the evaluation board uses numbers as identifiers to aid in the placement of matching components at both the rf input and rf output of the device. figure 37 and figure 38 show images of the board layout. rfin vcc3 vcc2 disable rfout 12 vbias 11 vcc 10 disable 9 rfin 1 2 3 4 adl5605 c out 8pf c2 100pf c1 100pf c in n/a c3 10pf c4 open c10 open c5 100pf c7 100pf c8 0.01f c9 10f rfout rfout rfout rfout 09353-036 13 8 14 7 15 6 16 5 nc nc nc nc nc nc nc nc c6 0.01f c11 10f c12 100pf c13 0.01f c14 10f l1 18nh l2 1.6nh vcc1 r4 open r1 0 ? r5 open r2 0 ? figure 36. evaluation board, 943 mhz frequency tuning band table 8. evaluation board configuration options, 943 mhz frequency tuning band component function/notes default value c1, c2 input/output dc blocking capacitors. c1, c2 = 100 pf c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14 power supply decoupling capacitors. power supp ly decoupling capacitors are required to filter out the high frequency noise on the power supply. the smallest capacitor should be the closest to the adl5605 . the main bias that goes through rfout is the most sensitive to noise because the bias is connected directly to the rf output. c3 = 10 pf c5, c7, c12 = 100 pf c6, c8, c13 = 0.01 f c9, c11, c14 = 10 f c4, c10 = open c in input matching capacitor. to match the adl5605 at the 943 mhz or 881 mhz frequency tuning band, c in is not required. for the 748 mhz frequency tuning band, c in is set at a specific distance from the device so that the microstrip line ca n act as inductance for the matching network (see table 7). if space is at a premium, an inductor can take the place of the microstrip line. c in = open c out output matching capacitor. the output match is set for 943 mhz and is easily changed for other frequency tuning bands. the tolerance of this capacitor should be tight. c out is set at a specific distance from the device so that th e microstrip line can act as inductance for the matching network (see table 7). if space is at a premium, an inductor can take the place of the microstrip line. a short length of low impedance line on the output is embedded in the match. c out = 8.0 pf hq l2 output matching inductor. the o utput match is set for 943 mhz an d is easily changed for other frequency tuning bands. a high q coilcraft inductor with tight tolerance is recommended. l2 = 1.6 nh hq l1 the main bias for the adl5605 comes through l1 to the output stage. l1 should be high impedance for the frequency of operation while providing low resistance for the dc current. the evaluation board uses a coilcraft 0603hp-18nx_lu inductor; this 18 nh inductor provides some of the match at 943 mhz. l1 = 18 nh r1, r2, r4, r5 to provide bias to all stages through just one supply, set r1 and r2 to 0 , and leave r4 and r5 open. to provide separate bias to stages, se t r1 and r2 to open and r4 and r5 to 0 . r1, r2 = 0 r4, r5 = open exposed paddle the paddle should be connected to both thermal and electrical ground.
adl5605 rev. 0 | page 17 of 20 09353-037 figure 37. evaluation board layout, top 09353-038 figure 38. evaluation board layout, bottom
adl5605 rev. 0 | page 18 of 20 outline dimensions 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indicator top view 4.00 bsc sq 3.75 bsc sq coplanarity 0.08 exposed pa d (bottom view) compliant to jedec standards mo-220-vggc 12 max 1.00 0.85 0.80 seating plane 0.35 0.30 0.25 0.80 max 0.65 typ 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indicator 0.50 0.40 0.30 0.25 min 2.50 2.35 sq 2.20 082008-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 39. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adl5605acpz-r7 ?40c to +85c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-10 ADL5605-EVALZ evaluation board 1 z = rohs compliant part.
adl5605 rev. 0 | page 19 of 20 notes
adl5605 rev. 0 | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09353-0-7/11(0)

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